A major obstacle which has confronted the prior art in improving the performance of large MOSFET arrays is the resistance of interconnection paths or buses to ground potential when they are implemented using state-of-the-art diffused or polycrystalline lines. The ohmic resistance of these lines causes an inverse relationship between the array size and its circuit performance parameters such as access time, noise tolerance, and temperature operating range. As the array size increases, the design of its cells and support circuits has to be compromised in order to account for resistance-induced ground shifts which cause random malfunctioning. The prior art has proposed low resistance buses to distribute power and ground to large scale integrated (LSI) circuitry. For instance, U.S. Pat. No. 3,808,475 discloses the addition of a metallic level for the sole purpose of distributing ground potential to circuit "macros." This is typical of the approach often used by the prior art, particularly in the case of bipolar LSI. This approach is expensive because of the fabrication cost of an extra metallic level and reductions in manufacturing yield by electrical shorts to other power distribution levels.
Thus, there is an economic incentive to solutions of the ground resistance problem that can be implemented without increasing the fabrication cost of the improved LSI chip.
In what follows, we propose a semiconductor ground distribution structure which substantially reduces the resistance to ground of devices belonging to an array. When said ground distribution is applied to MOSFET arrays fabricated from two layers of polysilicon material, it can be implemented using one of those polysilicon layers. Our invention then solves the ground resistance problem by capitalizing on already existing processes and hence it is cost effective.